Conventionally, higher capacity of a two-dimensional semiconductor memory device has been realized, by downscaling the circuit. However, because downscaling technology is, approaching a limit, a three-dimensional semiconductor memory device is being developed to realize even higher capacity. In the three-dimensional semiconductor memory device, a stacked body in which multiple electrode films are stacked is provided on a substrate; multiple semiconductor members that pierce the stacked body are provided; and memory cell transistors are formed at the crossing portions between the electrode films and the semiconductor member.
In the two-dimensional semiconductor memory device, the neutral threshold of the memory cell transistor is controlled by performing ion implantation into a semiconductor substrate used to form a channel. However, in the three-dimensional semiconductor memory device, it is difficult to introduce an impurity with high precision and at a low concentration into the semiconductor member used to form the channel. Therefore, it is difficult to control the neutral threshold of the memory cell transistor in the three-dimensional semiconductor memory device.